[V3] PCI: fu740: Drop to 2.5GT/s to fix initial device probing on some boards

[Ben Dooks]

On 23/03/2022 10:36, Alexandre Ghiti wrote:
> On 3/21/22 14:49, Alexandre Ghiti wrote:
>> Hi Ben,
>>
>> On 3/18/22 16:24, Ben Dooks wrote:
>>> The fu740 PCIe core does not probe any devices on the SiFive Unmatched
>>> board without this fix (or having U-Boot explicitly start the PCIe via
>>> either boot-script or user command). The fix is to start the link at
>>> 2.5GT/s speeds and once the link is up then change the maximum speed 
>>> back
>>> to the default.
>>>
>>> The U-Boot driver claims to set the link-speed to 2.5GT/s to get the 
>>> probe
>>> to work (and U-Boot does print link up at 2.5GT/s) in the following 
>>> code:
>>> https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/pci/pcie_dw_sifive.c?id=v2022.01#L271 
>>>
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks at codethink.co.uk>


[snip]

>>>     static int fu740_pcie_host_init(struct pcie_port *pp)
>>
>> +cc Maciej and David as there is this other fix that seems to do the 
>> same but differently, it's been under review for some time now: 
>> https://lore.kernel.org/all/20220302000043.GA662523@bhelgaas/t/
>>

I did have a quick look, but I think because we don't get any PCIe
probing at-all we don't even have a device to attach to.

>> I fell onto this issue recently, I'll give your patch and the above a 
>> try soon.
> 
> 
> FWIW, I have tested this and it solved my issue with nvme not being 
> probed, so:
> 
> Tested-by: Alexandre Ghiti <alexandre.ghiti at canonical.com>

Ok, great. Our test rig seems to be still working with this.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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