[PATCH v2 2/2] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode

[Marc Zyngier]

On 2022-03-01 17:13, Niklas Cassel wrote:
> From: Niklas Cassel <niklas.cassel at wdc.com>
> 
> When detecting a context for a privilege mode different from the 
> current
> running privilege mode, we simply skip to the next context register.
> 
> This means that we never clear the S-mode enable bits when running in
> M-mode.
> 
> On canaan k210, a bunch of S-mode interrupts are enabled by the 
> bootrom.
> These S-mode specific interrupts should never trigger, since we never 
> set
> the mie.SEIE bit in the parent interrupt controller (riscv-intc).
> 
> However, we will be able to see the mip.SEIE bit set as pending.
> 
> This isn't a good default when CONFIG_RISCV_M_MODE is set, since in 
> that
> case we will never enter a lower privilege mode (e.g. S-mode).
> 
> Let's clear the S-mode enable bits when running the kernel in M-mode, 
> such
> that we won't have a interrupt pending bit set, which we will never 
> clear.
> 
> Signed-off-by: Niklas Cassel <niklas.cassel at wdc.com>
> ---
>  drivers/irqchip/irq-sifive-plic.c | 26 +++++++++++++++++++++-----
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-sifive-plic.c
> b/drivers/irqchip/irq-sifive-plic.c
> index fc9da94eb816..e6193d66c0ae 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -81,17 +81,23 @@ static int plic_parent_irq __ro_after_init;
>  static bool plic_cpuhp_setup_done __ro_after_init;
>  static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
> 
> -static inline void plic_toggle(struct plic_handler *handler,
> -				int hwirq, int enable)
> +static inline void __plic_toggle(void __iomem *enable_base,
> +				 int hwirq, int enable)

While you're at it, please drop the inline attributes. They really
serve no purpose, as that's the job of the compiler.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...