[PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On 2022-06-29 14:41, Pavel Machek wrote:
> Hi!
> 
>> > >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>> > >>
>> > >>  struct plic_priv {
>> > >>         struct cpumask lmask;
>> > >>         struct irq_domain *irqdomain;
>> > >>         void __iomem *regs;
>> > >> +       u32 plic_quirks;
>> > >>  };
>> > >>
>> > >> What about something like above?
>> > >
>> > > LGTM.
>> > >
>> > > Marc suggested to make this unsigned long, but TBH, that won't make
>> > > much of a difference.  PLICs are present on RV32 SoCs, too, so you
>> > > cannot rely on having more than 32 bits anyway.
>> >
>> > But it will make a difference on a 64bit platform, as we want to
>> > use test_bit() and co to check for features.
>> >
>> Ok will change that to unsigned long and use the test_bit/set_bit 
>> instead.
> 
> Is there good enough reason for that? test_bit/... are when you need
> atomicity, and that's not the case here. Plain old & ... should be
> enough.

On any save architecture, '&' and test_bit() are the same thing.
Only RMW operations require atomicity.

'unsigned long' is is.

         M.
-- 
Jazz is not dead. It just smells funny...