[PATCH v2 08/16] riscv: dts: canaan: fix the k210's memory node.
Conor Dooley
mail at conchuod.ie
Mon Jun 27 12:39:56 PDT 2022
From: Conor Dooley <conor.dooley at microchip.com>
The k210 U-Boot port has been using the clocks defined in the
devicetree to bring up the board's SRAM, but this violates the
dt-schema. As such, move the clocks to a dedicated node with
the same compatible string. The regs property does not fit in
either node, so is replaced by comments.
Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
The corresponding U-Boot code seems to be:
static int sram_init(void)
{
int ret, i;
const char * const banks[] = { "sram0", "sram1", "aisram" };
ofnode memory;
struct clk clk;
/* Enable RAM clocks */
memory = ofnode_by_compatible(ofnode_null(), "canaan,k210-sram");
if (ofnode_equal(memory, ofnode_null()))
return -ENOENT;
for (i = 0; i < ARRAY_SIZE(banks); i++) {
ret = clk_get_by_name_nodev(memory, banks[i], &clk);
if (ret)
continue;
ret = clk_enable(&clk);
clk_free(&clk);
if (ret)
return ret;
}
return 0;
}
Which, without having the hardware etc, I suspect is likely to keep
working after the move.
---
arch/riscv/boot/dts/canaan/k210.dtsi | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 44d338514761..cd4eae82d8b2 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -69,11 +69,13 @@ cpu1_intc: interrupt-controller {
sram: memory at 80000000 {
device_type = "memory";
+ reg = <0x80000000 0x400000>, /* sram0 4 MiB */
+ <0x80400000 0x200000>, /* sram1 2 MiB */
+ <0x80600000 0x200000>; /* aisram 2 MiB */
+ };
+
+ sram_controller: memory-controller {
compatible = "canaan,k210-sram";
- reg = <0x80000000 0x400000>,
- <0x80400000 0x200000>,
- <0x80600000 0x200000>;
- reg-names = "sram0", "sram1", "aisram";
clocks = <&sysclk K210_CLK_SRAM0>,
<&sysclk K210_CLK_SRAM1>,
<&sysclk K210_CLK_AI>;
--
2.36.1
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