[PATCH v2 0/2] perf: RISC-V: fix access beyond allocated array

[Sergey Matyukevich]

Hi all,

These patches suggest some fixes and cleanups for the handling of pmu
counters. The first patch fixes access beyond the allocated pmu_ctr_list
array. The second patch fixes the counters mask sent to SBI firmware: it
excludes counters that were not fully specified by SBI firmware on init.

Initial attempt to fix access to the highest available has been reworked.
Now it is handled in the OpenSBI, see the following patch:
- https://patchwork.ozlabs.org/project/opensbi/patch/20220624110330.452640-1-geomatsi@gmail.com/

Regards,
Sergey

v1 -> v2:
- drop changes for access to the highest available counter as they are
  now handled on the OpenSBI side
- drop switch to IDR: in fact there is no need to handle non-contiguous
  counter ranges

Sergey Matyukevich (2):
  perf: RISC-V: fix access beyond allocated array
  perf: RISC-V: exclude invalid pmu counters from SBI calls

 drivers/perf/riscv_pmu_legacy.c |  4 ++--
 drivers/perf/riscv_pmu_sbi.c    | 24 ++++++++++++++----------
 include/linux/perf/riscv_pmu.h  |  2 +-
 3 files changed, 17 insertions(+), 13 deletions(-)

-- 
2.36.1