Tickless timer regression in v5.18.3 on riscv

[Eva Kotova]

On Thu, Jun 23, 2022 at 8:59 PM Anup Patel <anup at brainfault.org> wrote:
 > I suggest we introduce an optional "riscv,timer-always-on" DT
 > property for each HART. If all HART DT nodes have this property then
 > we don't set C3STOP flag in clockevent device, else we set it.

Is there any particular reason not to implement the opposite DT property 
"riscv,timer-s3stop" for timers that stop in suspend?
Right now, this patch breaks the behavior of previously fine working 
boards (worse sleep precision, higher idle consumption), and these 
boards have none of the mentioned issues, so why should they degrade 
after a kernel update?
The CLINT timer is already well-defined and worked for years, i don't 
see how suspend issues on particular hardware can justify going against 
the official spec.

I do really think this should be addressed by the platform SBI 
implementation (that's why SBI exists after all?..) or DT properties for 
suspend-affected hardware, not finding holes in SBI spec and introducing 
fragmentation in the SW ecosystem.