[PATCH 2/3] riscv: Implement Zicbom-based cache management operations

[Christoph Hellwig]

On Wed, Jun 15, 2022 at 06:56:40PM +0200, Heiko Stübner wrote:
> If I'm reading things correctly [0], the default for those functions
> is for those to be empty - but defined in the coherent case.

That's not the point.

Zicbom is just an extension that allows the CPU to support managing
cache state.  Non-coherent DMA is just one of the use cases there
are others like persistent memory.  And when a CPU core supports
Zicbom it might or might not have any non-coherent periphals.  Or
even some coherent and some non-coherent ones, something that
is pretty common in arm/arm64 CPUs, where PCIe is usually cache
coherent, but some other cheap periphals might not be.

That is why Linux ports require the plaform (usually through
DT or ACPI) to mark which devices are coherent and which ones
are not.