[PATCH 1/2] pwm: add microchip soft ip corePWM driver

Sun Jun 12 14:16:56 PDT 2022

On Sun, Jun 12, 2022 at 01:00:53PM +0000, Conor.Dooley at microchip.com wrote:
> Hey Uwe, one last one for ya..
> 
> On 08/06/2022 16:13, Uwe Kleine-König wrote:
> > Hello Conor,
> > 
> > On Wed, Jun 08, 2022 at 12:12:37PM +0000, Conor.Dooley at microchip.com wrote:
> >> On 07/06/2022 21:07, Uwe Kleine-König wrote:
> >>> On Tue, Jun 07, 2022 at 09:45:51AM +0100, Conor Dooley wrote:
> >>>> Add a driver that supports the Microchip FPGA "soft" PWM IP core.
> >>>>
> >>>> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> >>>> ---
> ---8<---
> >>>> +struct mchp_core_pwm_registers {
> >>>> +	u8 posedge;
> >>>> +	u8 negedge;
> >>>> +	u8 period_steps;
> >>>> +	u8 prescale;
> >>>
> >>> these are the four registers for each channel, right? Can you add a
> >>> short overview how these registers define the resulting output wave.
> >>
> >> Ehh, only the edges are per channel. Does that change anything about
> >> your feedback?
> >> I'll add an explanation for each, sure.
> > 
> > So the channels share the same period? If so you'll have to keep track
> > of which PWM channels are enabled and only change the period if no other
> > running channel is affected.
> 
> When I am capping the period (or not allowing it to be changed in this case
> here) should I correct the duty cycle so that the the ratio is preserved?

No, the thing to do is: Pick the biggest possible period not bigger
than the requested period. For that period pick the biggest possible
duty_cycle not bigger than the requested duty_cycle.

The focus here is to do something somewhat sensible and simple.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |
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