No subject

Myrtle Shah gatecat at ds0.me
Thu Jan 20 07:28:26 PST 2022

Previous message (by thread): [PATCH v3 0/6] Sparse HART id support
Next message (by thread): [PATCH 1/2] riscv: Fix XIP_FIXUP_FLASH_OFFSET
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

These are some initial patches to bugs I found attempting to
get a XIP kernel working on hardware:
 - 32-bit VexRiscv processor
 - kernel in SPI flash, at 0x00200000
 - 16MB of RAM at 0x10000000
 - MMU enabled
 
I still have some more debugging to do, but these at least
get the kernel as far as initialising the MMU, and I would
appreciate feedback if anyone else is working on RISC-V XIP.

Previous message (by thread): [PATCH v3 0/6] Sparse HART id support
Next message (by thread): [PATCH 1/2] riscv: Fix XIP_FIXUP_FLASH_OFFSET
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the linux-riscv mailing list