[PATCH 1/2] RISC-V: Better 'S' workaround

[Tsukasa OI]

This commit moves 'S' workaround and skips 'S' and 'U' "extensions"
(invalid as single-letter extensions) from riscv_isa (base ISA
extensions).

This commit is intended to be squashed into Atish's isa_framework_v4
PATCH 3/6.

Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
---
 arch/riscv/kernel/cpufeature.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c3ef55203117..b00ce81627a4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -113,15 +113,19 @@ void __init riscv_fill_hwcap(void)
 
 			switch (*ext) {
 			case 's':
-			case 'x':
-			case 'z':
 				/**
 				 * Workaround for invalid single-letter 's' (QEMU).
 				 * It works until multi-letter extension starting
 				 * with "Su" appears.
 				 */
-				if (*ext == 's' && ext[-1] != '_' && ext[1] == 'u')
+				if (ext[-1] != '_' && ext[1] == 'u') {
+					++isa;
+					ext_err = true;
 					break;
+				}
+				fallthrough;
+			case 'x':
+			case 'z':
 				ext_long = true;
 				/* Multi-letter extension must be delimited */
 				for (; *isa && *isa != '_'; ++isa)
-- 
2.32.0