[PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver

[Bin Meng]

Hi Sergey,

On 2022/12/23 4:06:23, "Sergey Matyukevich" <geomatsi at gmail.com> wrote:

>Hi Bin,
>
>>  RISC-V semihosting spec [1] is built on top of the existing Arm one;
>>  we can add RISC-V earlycon semihost driver easily.
>>
>>  This series refactors the existing driver a little bit, to move smh_putc()
>>  variants in respective arch's semihost.h, then we can implement RISC-V's
>>  version in the riscv arch directory.
>>
>>  Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1]
>>
>>  Changes in v3:
>>  - add #ifdef in the header to prevent from multiple inclusion
>>  - add forward-declare struct uart_port
>>  - add a Link tag in the commit message
>>
>>  Changes in v2:
>>  - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h"
>>  - Move the RISC-V implementation to semihost.h
>>
>>  Bin Meng (3):
>>    serial: earlycon-arm-semihost: Move smh_putc() variants in respective
>>      arch's semihost.h
>>    riscv: Implement semihost.h for earlycon semihost driver
>>    serial: Rename earlycon semihost driver
>>
>>   arch/arm/include/asm/semihost.h               | 30 +++++++++++++++++++
>>   arch/arm64/include/asm/semihost.h             | 24 +++++++++++++++
>>   arch/riscv/include/asm/semihost.h             | 26 ++++++++++++++++
>>   drivers/tty/serial/Kconfig                    | 14 ++++-----
>>   drivers/tty/serial/Makefile                   |  2 +-
>>   ...con-arm-semihost.c => earlycon-semihost.c} | 25 +---------------
>>   6 files changed, 89 insertions(+), 32 deletions(-)
>>   create mode 100644 arch/arm/include/asm/semihost.h
>>   create mode 100644 arch/arm64/include/asm/semihost.h
>>   create mode 100644 arch/riscv/include/asm/semihost.h
>>   rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (57%)
>
>Tested-by: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
>
>Applied the patches on top of Linux 6.1 and tested earlycon logs from
>RISC-V target in OpenOCD.
>

Thanks for your testing!

Regards,
Bin