[RFC PATCH 1/1] arch/riscv : Add support for Zba/Zbb/Zbc/Zbs ext in ISA realization
Conor Dooley
conor.dooley at microchip.com
Tue Dec 20 04:52:18 PST 2022
On Tue, Dec 20, 2022 at 12:02:36PM +0000, Ruinland Tsai wrote:
> arch/riscv : Add support for Zba/Zbb/Zbc/Zbs ext in ISA realization
s|arch/riscv :|riscv:
> This commit adds the ratified RISC-V Bitmanip 1.0.0 extensions
"add the ..."
> into the hadrware capability realization procedure.
hardware
>
> Thus, the print out of Zba/Zbb/Zbc/Zbs of /proc/cpuinfo could be
> matching the information provided in DT.
"Thus, the printout of ... from /proc/cpuinfo could match the
information..."
>
> Signed-off-by: Ruinland Tsai <ruinland.tsai at sifive.com>
> ---
> arch/riscv/Kconfig | 24 ++++++++++++++++++++++++
> arch/riscv/Makefile | 6 ++++++
> arch/riscv/include/asm/hwcap.h | 4 ++++
> arch/riscv/kernel/cpu.c | 4 ++++
> arch/riscv/kernel/cpufeature.c | 4 ++++
> 5 files changed, 42 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e2b656043abf..4f64d02d5208 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -447,6 +447,30 @@ config TOOLCHAIN_HAS_ZIHINTPAUSE
> depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zihintpause)
> depends on LLD_VERSION >= 150000 || LD_VERSION >= 23600
>
> +config TOOLCHAIN_HAS_ZBA
> + bool "Zba extension support for B extension on Address generation"
> + default y
> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
Surely all of these things need to check for linker support too, not
just cc? Consider a setup where CC is rather new, but the linker is
quite old. Does this not cause problems for Zb* as it did for
ZIHINTPAUSE?
> +config TOOLCHAIN_HAS_ZBB
> + bool "Zbb extension support for B extension on Basic bit-manipulation"
> + default y
> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb)
> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb)
> +
> +config TOOLCHAIN_HAS_ZBC
> + bool "Zbc extension support for B extension on Carry-less multiplication"
> + default y
> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbc)
> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc)
> +
> +config TOOLCHAIN_HAS_ZBS
> + bool "Zbs extension support for B extension on single-bit instruction"
> + default y
> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbs)
> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbs)
> +
> config FPU
> bool "FPU support"
> default y
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index faf2c2177094..635fc2642a5e 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -61,6 +61,12 @@ riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
> # Check if the toolchain supports Zicbom extension
> riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZICBOM) := $(riscv-march-y)_zicbom
>
> +# Check if the toolchain supports ratified B extensions
> +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZBA) := $(riscv-march-y)_zba
> +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZBB) := $(riscv-march-y)_zbb
> +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZBC) := $(riscv-march-y)_zbc
> +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZBS) := $(riscv-march-y)_zbs
> +
> # Check if the toolchain supports Zihintpause extension
> riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 86328e3acb02..baa51a282a69 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -55,6 +55,10 @@ extern unsigned long elf_hwcap;
> enum riscv_isa_ext_id {
> RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
> RISCV_ISA_EXT_SVPBMT,
> + RISCV_ISA_EXT_ZBA,
> + RISCV_ISA_EXT_ZBB,
> + RISCV_ISA_EXT_ZBC,
> + RISCV_ISA_EXT_ZBS,
> RISCV_ISA_EXT_ZICBOM,
> RISCV_ISA_EXT_ZIHINTPAUSE,
> RISCV_ISA_EXT_SSTC,
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 1b9a5a66e55a..70361105a612 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -166,6 +166,10 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
> + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
Exactly how uABI-y this array is may be up for debate so I'd rather not
add a whole load of items in in what may be an "incorrect" order.
https://lore.kernel.org/all/20221205144525.2148448-1-conor.dooley@microchip.com/
I'll make sure to go ping that one once the merge window closes so that
we have a definitive order in which things must be added.
Thanks,
Conor.
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 93e45560af30..ee536e08d197 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -224,6 +224,10 @@ void __init riscv_fill_hwcap(void)
> } else {
> SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
> + SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
> + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC);
> + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
> SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
> SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
> SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
> --
> 2.34.1
>
>
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>
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