[PATCH v2 7/9] clk: microchip: mpfs: re-parent the configurable clocks

[Stephen Boyd]

Quoting Conor Dooley (2022-04-11 01:59:15)
> Currently the mpfs clock driver uses a reference clock called the
> "msspll", set in the device tree, as the parent for the cpu/axi/ahb
> (config) clocks. The frequency of the msspll is determined by the FPGA
> bitstream & the bootloader configures the clock to match the bitstream.
> The real reference is provided by a 100 or 125 MHz off chip oscillator.
> 
> However, the msspll clock is not actually the parent of all clocks on
> the system - the reference clock for the rtc/mtimer actually has the
> off chip oscillator as its parent.
> 
> In order to fix this, add support for reading the configuration of the
> msspll & reparent the "config" clocks so that they are derived from
> this clock rather than the reference in the device tree.
> 
> Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
> Reviewed-by: Daire McNamara <daire.mcnamara at microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> 
> @Stephen/Mike: Is it acceptable to add the recalc rate without a set
> rate? If not lmk and I will add one.

Only recalc_rate is OK. It's like a read-only divider.