[PATCH v1] clk: microchip: mpfs: don't reset disabled peripherals

[Andrew Lunn]

On Fri, Apr 08, 2022 at 01:13:53PM +0000, Conor Dooley wrote:
> The current clock driver for PolarFire SoC puts the hardware behind
> "periph" clocks into reset if their clock is disabled. CONFIG_PM was
> recently added to the riscv defconfig and exposed issues caused by this
> behaviour, where the Cadence GEM was being put into reset between its
> bringup & the PHY bringup:
> 
> https://lore.kernel.org/linux-riscv/9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com/
> 
> Fix this by removing the reset enable/disable code from the driver &
> rely (for now) on the bootloader bringing peripherals out of reset
> during boot.

Maybe you should keep the clock enable -> disable reset part, and only
remove the clock disable -> assert reset part. You are making the
assumption that the bootloader disables reset on everything, when in
fact it could only disable resets on peripherals it needs, and it
needs the ethernet for TPTP boot.

What is your long term fix? It seems like you need to add a reset
controller. The macb already seems to support that:

macb_main.c:	/* Fully reset GEM controller at hardware level using zynqmp-reset driver,
macb_main.c:	ret = device_reset_optional(&pdev->dev);

So once you have it, it should be easy to wire up for this
peripheral. Once you have them all using the reset controller, you can
then remove all the reset code from the clock driver.

   Andrew