riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1

[Conor.Dooley at microchip.com]

On 06/04/2022 08:36, Conor Dooley wrote:
> On 05/04/2022 15:04, Andrew Lunn wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>>> [ 2.818894] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Generic PHY] (irq=POLL)
>>> [ 2.828915] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
>>> [11.045411] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
>>> [11.053247] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>>
>> You have a multi-part link. You need that the PHY reports the line
>> side is up. Put some printk in genphy_update_link() and look at
>> phydev->link. You also need that the SGMII link between the PHY and
>> the SoC is up. That is a bit harder to see, but try adding #define
>> DEBUG at the top of phylink.c and phy.c so you get additional debug
>> prints for the state machines.
> 
> Tracked the state of phydev->link in genphy_update_link, never saw a
> value other than 0.
> 
> Using the debug prints in phylink.c I got the following:
> [    3.230364] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL)
> [    3.240682] macb 20112000.ethernet eth0: phy: sgmii setting supported 0000000,00000000,000042ff advertising 0000000,00000000,000042ff
> [    3.252783] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
> [    3.259892] macb 20112000.ethernet eth0: major config sgmii
> [    3.265526] macb 20112000.ethernet eth0: phylink_mac_config: mode=phy/sgmii/Unknown/Unknown adv=0000000,00000000,00000000 pause=00 link=0 an=0
> [    3.279249] macb 20112000.ethernet eth0: phy link down sgmii/Unknown/Unknown/off
> 
> I couldn't see any prints out of phy.c

I think I have found the problem. While the SMGII clock is not in
Linux's remit, the mac clocks are. Without CONFIG_PM I see
the following, where 5 represents the clock for MAC1:

[    0.907959] mpfs_periph_clk_enable: 5
[    1.312955] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (00:04:a3:4d:4c:dc)
[    2.660376] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Generic PHY] (irq=POLL)
[    2.670400] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
[    6.789474] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off

With CONFIG_PM, the MAC1 clock gets disabled between mac and phy
bringup. 4 is the clock for the other MAC:

[    0.932598] mpfs_periph_clk_enable: 5
[    1.327876] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (00:04:a3:4d:4c:dc)
[    1.473632] mpfs_periph_clk_disable: 5
[    1.503327] mpfs_periph_clk_disable: 4
[    2.999528] mpfs_periph_clk_enable: 5
[    3.000300] macb 20112000.ethernet eth0: validation of sgmii with support 0000000,00000000,00006280 and advertisement 0000000,00000000,00004280 failed: -EINVAL
[    3.018612] macb 20112000.ethernet eth0: Could not attach PHY (-22)
[    3.143594] mpfs_periph_clk_disable: 5

However the clock driver is actually not only disabling the clock,
but also putting peripherals into reset when the clock to them is
disabled. Removing the reset gives:

[    0.934717] mpfs_periph_clk_enable: 5
[    1.326564] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (00:04:a3:4d:4c:dc)
[    1.473155] mpfs_periph_clk_disable: 5
[    1.502805] mpfs_periph_clk_disable: 4
[    3.006384] mpfs_periph_clk_enable: 5
[    3.007691] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Generic PHY] (irq=POLL)
[    3.021409] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
[    7.114710] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off


Thanks for your help in figuring this out, looks like the problem
is mine to fix :)

Thanks again,
Conor.