[PATCH v1 2/6] RISC-V: Match GCC's semantics for multiple -march instances

[Palmer Dabbelt]

GCC's semantics for "-march=X -march=Y" are that Y entirely overrides X,
but sparse takes the union of these two ISA strings.  This fixes the
behavior by setting, instead of oring, the flags whenever a base ISA is
encountered.  RISC-V ISA strings can only have a single base ISA, it's
not like x86 where the 64-bit ISA is an extension of the 32-bit ISA.

Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
---
 target-riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-riscv.c b/target-riscv.c
index f5cc6cc3..494c08db 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -56,7 +56,7 @@ static void parse_march_riscv(const char *arg)
 		size_t len = strlen(pat);
 
 		if (!strncmp(arg, pat, len)) {
-			riscv_flags |= basic_sets[i].flags;
+			riscv_flags = basic_sets[i].flags;
 			arg += len;
 			goto ext;
 		}
-- 
2.34.1