[PATCH v2 0/2] riscv: improve unaligned memory accesses
Chen Huang
chenhuang5 at huawei.com
Thu Sep 16 06:08:53 PDT 2021
The patchset improves RISCV unaligned memory accesses, selects
HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
of unaligned memory accesses.
If CPU don't support unaligned memory accesses for now, please
select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
don't support unaligned memory accesses, I don't choose the
CONFIG for them.
Changes since v1:
- As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
unaligned memory accesses, add an option for CPUs to choose it or not.
Chen Huang (2):
riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
riscv: Support DCACHE_WORD_ACCESS
arch/riscv/Kconfig | 5 ++++
arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
2 files changed, 42 insertions(+)
--
2.25.1
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