[SPAM] [PATCH 0/2] riscv: improve unaligned memory accesses

[Jisheng Zhang]

On Mon, 13 Sep 2021 12:19:54 +0000
Chen Huang <chenhuang5 at huawei.com> wrote:

> The RISCV ISA can support unaligned memory accesses, so the patchset
> selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS

NO, per the spec, "Even when misaligned loads and stores complete
successfully, these accesses might run extremely slowly depending on the
implementation". it's far away from "efficient"

> to improve the efficiency of unaligned memory accesses.
> 
> Chen Huang (2):
>   riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
>   riscv: Support DCACHE_WORD_ACCESS
> 
>  arch/riscv/Kconfig                      |  2 ++
>  arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
>  2 files changed, 38 insertions(+)
>