[PATCH] riscv: fix misalgned trap vector base address
palmer at dabbelt.com
Wed Oct 27 14:22:24 PDT 2021
On Sun, 17 Oct 2021 22:22:38 PDT (-0700), 181250012 at smail.nju.edu.cn wrote:
> * The trap vector marked by label .Lsecondary_park should align on a
> 4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
> and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
> Signed-off-by: Chen Lu <181250012 at smail.nju.edu.cn>
> arch/riscv/kernel/head.S | 1 +
> 1 file changed, 1 insertion(+)
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
> csrw CSR_SCRATCH, zero
> +.align 2
> /* We lack SMP support or have too many harts, so park this hart */
Thanks, this is on fixes (with some commit message cleanups).
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