[RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt

[Anup Patel]

On Mon, Oct 25, 2021 at 9:36 AM <wefu at redhat.com> wrote:
>
> From: Wei Fu <wefu at redhat.com>
>
> Previous patch has added svpbmt in arch/riscv and changed the
> DT mmu-type. Update dt-bindings related property here.
>
> Signed-off-by: Wei Fu <wefu at redhat.com>
> Co-developed-by: Guo Ren <guoren at kernel.org>
> Signed-off-by: Guo Ren <guoren at kernel.org>
> Cc: Anup Patel <anup at brainfault.org>
> Cc: Palmer Dabbelt <palmer at dabbelt.com>
> Cc: Rob Herring <robh+dt at kernel.org>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index e534f6a7cfa1..76f324d85e12 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -59,6 +59,11 @@ properties:
>        - riscv,sv48
>        - riscv,none
>
> +  mmu-supports-svpbmt:
> +    description:
> +      Describes the CPU's mmu-supports-svpbmt support
> +    $ref: '/schemas/types.yaml#/definitions/phandle'

There were various proposals from different folks in the previous
email threads.

I think most of us were converging on:
1) Don't modify "mmu-type" DT property for backward
compatibility
2) Add boolean DT property "riscv,svpmbt" under
"mmu" child DT node of each CPU DT node. Same will apply
to boolean DT property "riscv,svnapot" as well.

We also have bitmanip and vector broken down into smaller
extensions so grouping related extensions as separate DT node
under each CPU node will be more readable and easy to parse.

Regards,
Anup

> +
>    riscv,isa:
>      description:
>        Identifies the specific RISC-V instruction set architecture
> --
> 2.25.4
>