[PATCH] soc: add polarfire soc system controller

Thu Oct 21 09:00:33 PDT 2021

On Thu, 21 Oct 2021 06:13:35 PDT (-0700), Conor.Dooley at microchip.com wrote:
> On 05/10/2021 13:47, conor.dooley at microchip.com wrote:
>> From: Conor Dooley <conor.dooley at microchip.com>
>>
>> This driver provides an interface for other drivers to access the
>> functions of the system controller on the Microchip PolarFire SoC.
>>
>> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> Is there some extra CCs that I am missing on this patch that weren't 
> picked up by getmaintainers,
> and/or am I mistaken in thinking that the soc tree is arm only?

+Arnd, Olof, and the SOC list.  They probably understand this better 
than I do, we're kind of new to having SOCs in RISC-V land.

I guess I was assuming that someone maintained drivers/soc, but from 
poking around it seems like there's no entry for it and instead it's 
just a bunch of entries for the sub-directories.  As a result the 
scripts aren't picking up anyone to send these too, and I'd assuming 
that because they're not in arch/riscv that they're not for the RISC-V 
tree.

That said, it looks like I put the Kendryte stuff in there (so sorry if 
I screwed anything up).  I'm happy to take these via the RISC-V tree as 
well, I'm assuming that means there should be a MAINTAINERS entry for 
this new sub-directory so changes to it are less likely to get lost.  
Sorry if I was confusing before, I guess I forgot about how this fits 
together.

Arnd: aside from the lack of a maintainer, these generally look fine to 
me.  LMK if you were expecting this kind of stuff to go through the 
RISC-V tree.

Conor: if you're not comfortable maintaining this then I'm OK signing up 
for it.  I certainly don't want to maintain all RISC-V SOC drivers, but 
I'm vaguely responsible for this one so I'm not opposed to it.  
Obviously preferable on my end to have less of that, though, as it can 
get out of hand pretty quickly.

>> ---
>>   drivers/soc/Kconfig                         |   1 +
>>   drivers/soc/Makefile                        |   1 +
>>   drivers/soc/microchip/Kconfig               |  10 ++
>>   drivers/soc/microchip/Makefile              |   1 +
>>   drivers/soc/microchip/mpfs-sys-controller.c | 119 ++++++++++++++++++++
>>   5 files changed, 132 insertions(+)
>>   create mode 100644 drivers/soc/microchip/Kconfig
>>   create mode 100644 drivers/soc/microchip/Makefile
>>   create mode 100644 drivers/soc/microchip/mpfs-sys-controller.c
>>
>> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
>> index e8a30c4c5aec..b33142e020e0 100644
>> --- a/drivers/soc/Kconfig
>> +++ b/drivers/soc/Kconfig
>> @@ -12,6 +12,7 @@ source "drivers/soc/imx/Kconfig"
>>   source "drivers/soc/ixp4xx/Kconfig"
>>   source "drivers/soc/litex/Kconfig"
>>   source "drivers/soc/mediatek/Kconfig"
>> +source "drivers/soc/microchip/Kconfig"
>>   source "drivers/soc/qcom/Kconfig"
>>   source "drivers/soc/renesas/Kconfig"
>>   source "drivers/soc/rockchip/Kconfig"
>> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
>> index a05e9fbcd3e0..e3be151e391e 100644
>> --- a/drivers/soc/Makefile
>> +++ b/drivers/soc/Makefile
>> @@ -17,6 +17,7 @@ obj-y				+= ixp4xx/
>>   obj-$(CONFIG_SOC_XWAY)		+= lantiq/
>>   obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/
>>   obj-y				+= mediatek/
>> +obj-y				+= microchip/
>>   obj-y				+= amlogic/
>>   obj-y				+= qcom/
>>   obj-y				+= renesas/
>> diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig
>> new file mode 100644
>> index 000000000000..eb656b33156b
>> --- /dev/null
>> +++ b/drivers/soc/microchip/Kconfig
>> @@ -0,0 +1,10 @@
>> +config POLARFIRE_SOC_SYS_CTRL
>> +	tristate "POLARFIRE_SOC_SYS_CTRL"
>> +	depends on POLARFIRE_SOC_MAILBOX
>> +	help
>> +	  This driver adds support for the PolarFire SoC (MPFS) system controller.
>> +
>> +	  To compile this driver as a module, choose M here. the
>> +	  module will be called mpfs_system_controller.
>> +
>> +	  If unsure, say N.
>> diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile
>> new file mode 100644
>> index 000000000000..14489919fe4b
>> --- /dev/null
>> +++ b/drivers/soc/microchip/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL)	+= mpfs-sys-controller.o
>> diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c
>> new file mode 100644
>> index 000000000000..3cfee997fa59
>> --- /dev/null
>> +++ b/drivers/soc/microchip/mpfs-sys-controller.c
>> @@ -0,0 +1,119 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Microchip PolarFire SoC (MPFS) system controller driver
>> + *
>> + * Copyright (c) 2020 Microchip Corporation. All rights reserved.
>> + *
>> + * Author: Conor Dooley <conor.dooley at microchip.com>
>> + *
>> + */
>> +
>> +#include <linux/slab.h>
>> +#include <linux/module.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/mailbox_client.h>
>> +#include <linux/platform_device.h>
>> +#include <soc/microchip/mpfs.h>
>> +
>> +static DEFINE_MUTEX(transaction_lock);
>> +
>> +struct mpfs_sys_controller {
>> +	struct mbox_client client;
>> +	struct mbox_chan *chan;
>> +	struct completion c;
>> +	u32 enabled;
>> +};
>> +
>> +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg)
>> +{
>> +	int ret;
>> +
>> +	mutex_lock_interruptible(&transaction_lock);
>> +
>> +	reinit_completion(&mpfs_client->c);
>> +
>> +	ret = mbox_send_message(mpfs_client->chan, msg);
>> +	if (ret >= 0) {
>> +		if (wait_for_completion_timeout(&mpfs_client->c, HZ)) {
>> +			ret = 0;
>> +		} else {
>> +			ret = -ETIMEDOUT;
>> +			dev_warn(mpfs_client->client.dev, "MPFS sys controller transaction timeout\n");
>> +		}
>> +	} else {
>> +		dev_err(mpfs_client->client.dev,
>> +			"mpfs sys controller transaction returned %d\n", ret);
>> +	}
>> +
>> +	mutex_unlock(&transaction_lock);
>> +
>> +	return ret;
>> +}
>> +EXPORT_SYMBOL(mpfs_blocking_transaction);
>> +
>> +static void rx_callback(struct mbox_client *client, void *msg)
>> +{
>> +	struct mpfs_sys_controller *mpfs_client =
>> +		container_of(client, struct mpfs_sys_controller, client);
>> +
>> +	complete(&mpfs_client->c);
>> +}
>> +
>> +static int mpfs_sys_controller_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct mpfs_sys_controller *mpfs_client;
>> +
>> +	mpfs_client = devm_kzalloc(dev, sizeof(*mpfs_client), GFP_KERNEL);
>> +	if (!mpfs_client)
>> +		return -ENOMEM;
>> +
>> +	mpfs_client->client.dev = dev;
>> +	mpfs_client->client.rx_callback = rx_callback;
>> +	mpfs_client->client.tx_block = 1U;
>> +
>> +	mpfs_client->chan = mbox_request_channel(&mpfs_client->client, 0);
>> +	if (IS_ERR(mpfs_client->chan))
>> +		return dev_err_probe(dev, PTR_ERR(mpfs_client->chan),
>> +				     "Failed to get mbox channel\n");
>> +
>> +	init_completion(&mpfs_client->c);
>> +
>> +	platform_set_drvdata(pdev, mpfs_client);
>> +
>> +	dev_info(&pdev->dev, "Registered MPFS system controller driver\n");
>> +
>> +	return 0;
>> +}
>> +
>> +struct mpfs_sys_controller *
>> +mpfs_sys_controller_get(struct device_node *mss_node)
>> +{
>> +	struct platform_device *pdev = of_find_device_by_node(mss_node);
>> +
>> +	if (!pdev)
>> +		return NULL;
>> +
>> +	return platform_get_drvdata(pdev);
>> +}
>> +EXPORT_SYMBOL(mpfs_sys_controller_get);
>> +
>> +static const struct of_device_id mpfs_sys_controller_of_match[] = {
>> +	{.compatible = "microchip,polarfire-soc-sys-controller", },
>> +	{},
>> +};
>> +MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match);
>> +
>> +static struct platform_driver mpfs_sys_controller_driver = {
>> +	.driver = {
>> +		.name = "mpfs-sys-controller",
>> +		.of_match_table = mpfs_sys_controller_of_match,
>> +	},
>> +	.probe = mpfs_sys_controller_probe,
>> +};
>> +module_platform_driver(mpfs_sys_controller_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_AUTHOR("Conor Dooley <conor.dooley at microchip.com>");
>> +MODULE_DESCRIPTION("MPFS system controller driver");
> 
> 