[PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support
maz at kernel.org
Wed Oct 20 06:34:05 PDT 2021
On Tue, 19 Oct 2021 14:27:02 +0100,
Guo Ren <guoren at kernel.org> wrote:
> On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier <maz at kernel.org> wrote:
> > On Tue, 19 Oct 2021 10:33:49 +0100,
> > Guo Ren <guoren at kernel.org> wrote:
> > > > If you have an 'automask' behavior and yet the HW doesn't record this
> > > > in a separate bit, then you need to track this by yourself in the
> > > > irq_eoi() callback instead. I guess that you would skip the write to
> > > > the CLAIM register in this case, though I have no idea whether this
> > > > breaks
> > > > the HW interrupt state or not.
> > > The problem is when enable bit is 0 for that irq_number,
> > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect
> > > the hw state machine. Then this irq would enter in ack state and no
> > > continues irqs could come in.
> > Really? This means that you cannot mask an interrupt while it is being
> > handled? How great...
> If the completion ID does not match an interrupt source that is
> currently enabled for the target, the completion is silently ignored.
> So, C9xx completion depends on enable-bit.
Is that what the PLIC spec says? Or what your implementation does? I
can understand that one implementation would be broken, but if the
PLIC architecture itself is broken, that's far more concerning.
Without deviation from the norm, progress is not possible.
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