[RFC PATCH v4 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings
Rob Herring
robh at kernel.org
Fri Oct 8 13:02:48 PDT 2021
On Thu, Oct 07, 2021 at 06:06:30PM +0530, Anup Patel wrote:
> We add DT bindings documentation for the ACLINT MTIMER device
> found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <anup.patel at wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
> .../bindings/timer/riscv,aclint-mtimer.yaml | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 000000000000..ebb7e81a5a12
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT M-level Timer
> +
> +maintainers:
> + - Anup Patel <anup.patel at wdc.com>
> +
> +description:
You need '|' if you want to maintain the paragraphs.
> + RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined
> + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The
> + ACLINT MTIMER device is documented in the RISC-V ACLINT specification found
> + at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> + The ACLINT MTIMER device directly connects to the M-level timer interrupt
> + lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local
> + interrupt controller is the parent interrupt controller for the ACLINT
> + MTIMER device.
> +
> + The clock frequency of ACLINT is specified via "timebase-frequency" DT
> + property of "/cpus" DT node. The "timebase-frequency" DT property is
> + described in Documentation/devicetree/bindings/riscv/cpus.yaml
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - sifive,fu540-c000-aclint-mtimer
> + - const: riscv,aclint-mtimer
> +
> + description:
> + Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer".
> +
> + reg:
> + description: |
> + Specifies base physical address(s) of the MTIME register and MTIMECMPx
> + registers. The 1st region is the MTIME register base and size. The 2nd
> + region is the MTIMECMPx registers base and size.
> + minItems: 2
> + maxItems: 2
All this can be expressed as:
items:
- description: The MTIME registers
- description: The MTIMECMPx registers
'reg' is always the physical address and size, so no need to redefine
common properties.
> +
> + interrupts-extended:
> + minItems: 1
> + maxItems: 4095
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> +
> +examples:
> + - |
> + timer at 2004000 {
> + compatible = "sifive,fu540-c000-aclint-mtimer", "riscv,aclint-mtimer";
> + reg = <0x200bff8 0x8>,
> + <0x2004000 0x7ff8>;
> + interrupts-extended = <&cpu1intc 7>,
> + <&cpu2intc 7>,
> + <&cpu3intc 7>,
> + <&cpu4intc 7>;
> + };
> +...
> --
> 2.25.1
>
>
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