[PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node

[Conor.Dooley at microchip.com]

On 26/11/2021 10:16, conor wrote:
> On 26/11/2021 09:48, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know 
>> the content is safe
>>
>> On 25/11/2021 16:31, Geert Uytterhoeven wrote:
>>> "make dtbs_check" reports:
>>>
>>>      arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: 
>>> soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 
>>> 'clock-frequency': [[600000000]], 'clock-output-names': 
>>> ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 
>>> 'object'}
>>>        From schema: dtschema/schemas/simple-bus.yaml
>>>
>>> Fix this by moving the node out of the "soc" subnode.
>>> While at it, rename it to "msspllclk", and drop the now superfluous
>>> "clock-output-names" property.
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert at linux-m68k.org>
>>> ---
>>>   arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 13 ++++++-------
>>>   1 file changed, 6 insertions(+), 7 deletions(-)
>>>
>>
>> It is also logical because refclk usually is not a property of the SoC.
>> It actually might be a property of board...
> This is one of the fun FPGAisms like the GPIO interrupt configuration. 
> This clock setting is determined by what design has been loaded onto the 
> FPGA - the msspll outputs are configurable, I could redo my FPGA design 
> and change this to 500 MHz etc. In turn the msspll clock is set by 
> another clock source that is actually on the board of either 100 or 125 
> MHz.
> 
> Since it's not set at bitstream programming time, I would agree that 
> that property should be moved to out of mpfs.dtsi.
Since it's not set **UNTIL** bitstream programming time

>>
>>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski at canonical.com>
>>
>>
>> Best regards,
>> Krzysztof
>>
>