[PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events

[Nikita Shubin]

Hello Mario!

On Mon, 22 Nov 2021 15:24:08 +0000
João Mário Domingos <joao.mario at tecnico.ulisboa.pt> wrote:

> On Wed, Nov 17, 2021 at 02:25:39PM +0300, Nikita Shubin wrote:
> > On Tue, 16 Nov 2021 15:48:12 +0000
> > João Mário Domingos <joao.mario at tecnico.ulisboa.pt> wrote:
> > 
> > Hello Mario!
> >   
> Hello Nikita!
> > > +  {
> > > +    "EventName": "UTLB_MISS",
> > > +    "EventCode": "0x0002002",
> > > +    "BriefDescription": "UTLB miss"
> > > +  }  
> > 
> > I don't see such thing in FU740 v1p3 manual - am i missing
> > something ?  
> You are absolutelly right, there is no reference to the L2 cache
> (Unified Cache) TLB misses event in the FU740 v1p3 manual. But
> considering that the FU740 is composed of 1 S7 and 4 U74 cores, I
> used the U74 core complex manual
> [https://www.starfivetech.com/uploads/u74_core_complex_manual_21G1.pdf]
> as the source for events. Did you test the utlb_miss event, and does
> it work in your board?

Thank you for pointing this out, it works indeed. Unfortunately not the
first inexactness in the FU740 v1p3 manual.

> 
> Best,
> João Mário
> > 
> > Yours,
> > Nikita Shubin
> > 
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