[PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features.
Greentime Hu
greentime.hu at sifive.com
Tue Nov 9 01:48:18 PST 2021
This patch is used to detect vector support status of CPU and use
riscv_vsize to save the size of all the vector registers. It assumes
all harts has the same capabilities in SMP system.
[guoren at linux.alibaba.com: add has_vector checking]
Signed-off-by: Greentime Hu <greentime.hu at sifive.com>
Co-developed-by: Guo Ren <guoren at linux.alibaba.com>
Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen at sifive.com>
Signed-off-by: Vincent Chen <vincent.chen at sifive.com>
---
arch/riscv/kernel/cpufeature.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 7069e55335d0..8e7557980faf 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -21,6 +21,11 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
#ifdef CONFIG_FPU
__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
#endif
+#ifdef CONFIG_VECTOR
+#include <asm/vector.h>
+__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector);
+unsigned long riscv_vsize __read_mostly;
+#endif
/**
* riscv_isa_extension_base() - Get base extension word
@@ -149,4 +154,12 @@ void __init riscv_fill_hwcap(void)
if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
static_branch_enable(&cpu_hwcap_fpu);
#endif
+
+#ifdef CONFIG_VECTOR
+ if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+ static_branch_enable(&cpu_hwcap_vector);
+ /* There are 32 vector registers with vlenb length. */
+ riscv_vsize = csr_read(CSR_VLENB) * 32;
+ }
+#endif
}
--
2.31.1
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