[PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio
Krzysztof Kozlowski
krzysztof.kozlowski at canonical.com
Mon Nov 8 13:22:55 PST 2021
On 08/11/2021 16:05, conor.dooley at microchip.com wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> Add device tree bindings for the gpio controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> .../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++
> 1 file changed, 108 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>
> diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> new file mode 100644
> index 000000000000..067019ddc1f7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS GPIO Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <conor.dooley at microchip.com>
> +
> +description: |
> + This GPIO controller is found on the Microchip PolarFire SoC.
If "Microchip MPFS" means "Microchip PolarFire SoC", then this is
duplicating the title. Similarly to your previous patches. Skip it then,
there is no point to have descriptions which are obvious or duplicating
existing information.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - microchip,mpfs-gpio
> + - microsemi,ms-pf-mss-gpio
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description:
> + Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
> + minItems: 1
> + maxItems: 32
> +
> + interrupt-controller: true
> +
> + clocks:
> + maxItems: 1
> +
> + "#gpio-cells":
> + const: 2
> +
> + ngpios:
> + description:
> + The number of GPIOs available.
> + minimum: 1
> + maximum: 32
> + default: 32
> +
> + gpio-controller: true
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - "#interrupt-cells"
> + - "#gpio-cells"
> + - gpio-controller
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + gpio2: gpio at 20122000 {
> + compatible = "microchip,mpfs-gpio";
> + reg = <0x0 0x20122000 0x0 0x1000>;
> + clocks = <&clkcfg CLK_GPIO2>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
Skip status=disabled.
> + };
> + };
> +...
>
Best regards,
Krzysztof
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