[PATCH bpf-next] riscv, bpf: Fix RV32 broken build, and silence RV64 warning

Daniel Borkmann daniel at iogearbox.net
Fri Nov 5 08:59:45 PDT 2021


On 11/3/21 2:35 PM, Björn Töpel wrote:
> On Wed, 3 Nov 2021 at 14:15, Daniel Borkmann <daniel at iogearbox.net> wrote:
>> On 11/3/21 12:54 PM, Björn Töpel wrote:
>>> Commit 252c765bd764 ("riscv, bpf: Add BPF exception tables") only
>>> addressed RV64, and broke the RV32 build [1]. Fix by gating the exception
>>> tables code with CONFIG_ARCH_RV64I.
>>>
>>> Further, silence a "-Wmissing-prototypes" warning [2] in the RV64 BPF
>>> JIT.
>>>
>>> [1] https://lore.kernel.org/llvm/202111020610.9oy9Rr0G-lkp@intel.com/
>>> [2] https://lore.kernel.org/llvm/202110290334.2zdMyRq4-lkp@intel.com/
>>>
>>> Fixes: 252c765bd764 ("riscv, bpf: Add BPF exception tables")
>>> Signed-off-by: Björn Töpel <bjorn at kernel.org>
>>> ---
>>> Tong/Daniel: The RV32 build has been broken since Thursday. I'll try
>>> to fast-track a bit, and commit a quick-fix for it. Hope that's OK
>>> with you, Tong!
>>>
>>> I've verified the build on my machine using riscv32 GCC 9.3.0 and
>>> riscv64 GCC 11.2.0.
>>
>> Thanks for the fix Bjorn!
>>
[...]
>>> +int rv_bpf_fixup_exception(const struct exception_table_entry *ex,
>>> +                             struct pt_regs *regs);
>>
>> I'm okay to take this as a quick fix, but if its not too much hassle, could we add a
>> arch/riscv/include/asm/extable.h in similar fashion like arm64 or x86 where we move
>> the ex_handler_bpf() signature there, did you have a chance to check?
> 
> OK! I've not looked into it yet!
> 
> There's a patch out from Jisheng on the RV list, which is starting
> some consolidation work [1].
> 
> @Jisheng What do you think about adding type/handlers [2,3] as
> arm64/x86 recently did, to your series?

Fyi, Bjorn, took your fix into bpf so we can move forward wrt broken build & warning
given its small anyway and I'm doing bpf PR very soon today. Either way, Jisheng, you
or Tong can follow-up looking into the extable streamlining wrt arm64/x86. Thanks!

> [1] https://lore.kernel.org/linux-riscv/20211022001957.1eba8f04@xhacker/
> [2] https://lore.kernel.org/linux-arm-kernel/20211019160219.5202-11-mark.rutland@arm.com/
> [3] https://lore.kernel.org/lkml/20210908132525.211958725@linutronix.de/



More information about the linux-riscv mailing list