[PATCH v2 0/5] riscv: introduce alternative mechanism to apply errata patches

[Vincent Chen]

With the emergence of more and more RISC-V CPUs, the request for how to
upstream the vendor errata patch may gradually appear. In order to resolve
this issue, this patch introduces the alternative mechanism from ARM64 and
x86 to enable the kernel to patch code at runtime according to the
manufacturer information of the running CPU. The main purpose of this patch
set is to propose a framework to apply vendor's errata solutions. Based on
this framework, it can be ensured that the errata only applies to the
specified CPU cores. Other CPU cores do not be affected. Therefore, some
complicated scenarios are unsupported in this patch set, such as patching
code to the kernel module, doing relocation in patching code, and
heterogeneous CPU topology.

In the "alternative" scheme, Users could use the macro ALTERNATIVE to apply
an errata to the existing code flow. In the macro ALTERNATIVE, users need
to specify the manufacturer information (vendor id, arch id, and implement
id) for this errata. Therefore, kernel will know this errata is suitable
for which CPU core. During the booting procedure, kernel will select the
errata required by the CPU core and then patch it. It means that the kernel
only applies the errata to the specified CPU core. In this case, the
vendor's errata does not affect each other at runtime. The above patching
procedure only occurs during the booting phase, so we only take the
overhead of the "alternative" mechanism once.

This "alternative" mechanism is enabled by default to ensure that all
required errata will be applied. However, users can disable this feature by
the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE".

The last two patches are to apply the SiFive CIP-453 and CIP-1200 errata by
this "alternative" scheme. Therefore, they can be regarded as examples.
According to the results of running this image on the QEMU virt platform,
kernel does not apply this errata at run-time because the CPU manufacturer
information does not match the specified SiFive CPU core. Therefore, these
errata does not affect any CPU core except for the specified SiFive cores.

Changes in v2 patch:
1. Display a warning message if Kernel finds the required errata is missing
2. Provide sample code for a vendor who wants to append its errata
3. Create a new patch to workaound SiFive errata cip-1200
4. Code refinement

Vincent Chen (5):
  riscv: Add 3 SBI wrapper functions to get cpu manufacturer information
  riscv: Introduce alternative mechanism to apply errata solution
  riscv: sifive: Add SiFive alternative ports
  riscv: sifive: Apply errata "cip-453" patch
  riscv: sifive: Apply errata "cip-1200" patch

 arch/riscv/Kconfig                          |   1 +
 arch/riscv/Kconfig.erratas                  |  45 +++++++++
 arch/riscv/Kconfig.socs                     |   1 +
 arch/riscv/Makefile                         |   1 +
 arch/riscv/errata/Makefile                  |   2 +
 arch/riscv/errata/alternative.c             |  74 +++++++++++++++
 arch/riscv/errata/sifive/Makefile           |   2 +
 arch/riscv/errata/sifive/errata.c           | 105 ++++++++++++++++++++
 arch/riscv/errata/sifive/errata_cip_453.S   |  38 ++++++++
 arch/riscv/include/asm/alternative-macros.h | 142 ++++++++++++++++++++++++++++
 arch/riscv/include/asm/alternative.h        |  39 ++++++++
 arch/riscv/include/asm/asm.h                |   1 +
 arch/riscv/include/asm/csr.h                |   3 +
 arch/riscv/include/asm/errata_list.h        |  39 ++++++++
 arch/riscv/include/asm/sbi.h                |   3 +
 arch/riscv/include/asm/sections.h           |   1 +
 arch/riscv/include/asm/tlbflush.h           |   3 +-
 arch/riscv/include/asm/vendorid_list.h      |  10 ++
 arch/riscv/kernel/entry.S                   |   6 +-
 arch/riscv/kernel/sbi.c                     |  15 +++
 arch/riscv/kernel/smpboot.c                 |   4 +
 arch/riscv/kernel/vmlinux.lds.S             |   7 ++
 22 files changed, 539 insertions(+), 3 deletions(-)
 create mode 100644 arch/riscv/Kconfig.erratas
 create mode 100644 arch/riscv/errata/Makefile
 create mode 100644 arch/riscv/errata/alternative.c
 create mode 100644 arch/riscv/errata/sifive/Makefile
 create mode 100644 arch/riscv/errata/sifive/errata.c
 create mode 100644 arch/riscv/errata/sifive/errata_cip_453.S
 create mode 100644 arch/riscv/include/asm/alternative-macros.h
 create mode 100644 arch/riscv/include/asm/alternative.h
 create mode 100644 arch/riscv/include/asm/errata_list.h
 create mode 100644 arch/riscv/include/asm/vendorid_list.h

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2.7.4