[RFC patch 2/4] riscv: Get CPU manufacturer information

[Damien Le Moal]

On 2021/03/09 10:25, Vincent Chen wrote:
>>>  #endif /* _ASM_RISCV_PROCESSOR_H */
>>> diff --git a/arch/riscv/include/asm/soc.h b/arch/riscv/include/asm/soc.h
>>> index f494066051a2..03dee6db404c 100644
>>> --- a/arch/riscv/include/asm/soc.h
>>> +++ b/arch/riscv/include/asm/soc.h
>>> @@ -10,6 +10,7 @@
>>>  #include <linux/of.h>
>>>  #include <linux/linkage.h>
>>>  #include <linux/types.h>
>>> +#include <asm/hwcap.h>
>>>
>>>  #define SOC_EARLY_INIT_DECLARE(name, compat, fn)                     \
>>>       static const struct of_device_id __soc_early_init__##name       \
>>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>>> index ac202f44a670..389162ee19ea 100644
>>> --- a/arch/riscv/kernel/cpufeature.c
>>> +++ b/arch/riscv/kernel/cpufeature.c
>>> @@ -12,6 +12,8 @@
>>>  #include <asm/hwcap.h>
>>>  #include <asm/smp.h>
>>>  #include <asm/switch_to.h>
>>> +#include <asm/sbi.h>
>>> +#include <asm/csr.h>
>>>
>>>  unsigned long elf_hwcap __read_mostly;
>>>
>>> @@ -22,6 +24,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
>>>  bool has_fpu __read_mostly;
>>>  #endif
>>>
>>> +struct cpu_manufacturer_info_t cpu_mfr_info;
>>> +
>>>  /**
>>>   * riscv_isa_extension_base() - Get base extension word
>>>   *
>>> @@ -149,3 +153,16 @@ void riscv_fill_hwcap(void)
>>>               has_fpu = true;
>>>  #endif
>>>  }
>>> +
>>> +void riscv_fill_cpu_manufacturer_info(void)
>>> +{
>>> +#ifndef CONFIG_RISCV_M_MODE
>>> +     cpu_mfr_info.vendor_id = sbi_get_vendorid();
>>> +     cpu_mfr_info.arch_id = sbi_get_archid();
>>> +     cpu_mfr_info.imp_id = sbi_get_impid();
>>> +#else
>>> +     cpu_mfr_info.vendor_id = csr_read(CSR_MVENDORID);
>>> +     cpu_mfr_info.arch_id = csr_read(CSR_MARCHID);
>>> +     cpu_mfr_info.imp_id = csr_read(CSR_MIMPID);
>>> +#endif
>>
>> Why ? reading the registers will work with M-Mode too. It was there before when
>> we temporarily had the builtin DTB lookup based on vendor/arch/imp (see defunct
>> soc_lookup_builtin_dtb() in 5.11).
>>
> Sorry, I cannot fully catch what you mean.
> I agree that reading these registers will work with M-Mode, so I used
> the macro csr_read() to read these three registers when the kernel run
> in the M-mode.
> The definition of csr_read() is here:
> #define csr_read(csr)                                           \
> ({                                                              \
>         register unsigned long __v;                             \
>         __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)        \
>                               : "=r" (__v) :                    \
>                               : "memory");                      \
>         __v;                                                    \
> })
> I guess that #if"n"def CONFIG_RISCV_M_MODE may mislead you. #ifndef is
> really unfriendly to read. I will change #ifndef to #ifdef in my next
> version patch.

You are right. I totally misread this :) It was my morning and I needed more
coffee ! Apologies for the noise. This looks fine.

> 
> 
>>> +}
>>> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
>>> index e85bacff1b50..03621ce9092c 100644
>>> --- a/arch/riscv/kernel/setup.c
>>> +++ b/arch/riscv/kernel/setup.c
>>> @@ -278,6 +278,8 @@ void __init setup_arch(char **cmdline_p)
>>>  #endif
>>>
>>>       riscv_fill_hwcap();
>>> +
>>
>> Nit: I do not think the white libe is really necessary here.
>>
> OK, I will remove it.
>>> +     riscv_fill_cpu_manufacturer_info();
>>>  }
>>>
>>>  static int __init topology_init(void)
>>> diff --git a/arch/riscv/kernel/soc.c b/arch/riscv/kernel/soc.c
>>> index a0516172a33c..58f6fd91743a 100644
>>> --- a/arch/riscv/kernel/soc.c
>>> +++ b/arch/riscv/kernel/soc.c
>>> @@ -6,6 +6,7 @@
>>>  #include <linux/libfdt.h>
>>>  #include <linux/pgtable.h>
>>>  #include <asm/soc.h>
>>> +#include <asm/hwcap.h>
>>
>> Why is this necessary ?
> 
> I forgot to remove it when doing code cleanup. Thank you for the
> reminder. I will remove it
> 


-- 
Damien Le Moal
Western Digital Research