[GIT PULL] RISC-V Fixes for 5.13-rc7

[Palmer Dabbelt]

The following changes since commit 0ddd7eaffa644baa78e247bbd220ab7195b1eed6:

  riscv: Fix BUILTIN_DTB for sifive and microchip soc (2021-06-11 21:07:09 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.13-rc7

for you to fetch changes up to 7ede12b01b59dc67bef2e2035297dd2da5bfe427:

  riscv: dts: fu740: fix cache-controller interrupts (2021-06-19 00:11:53 -0700)

----------------------------------------------------------------
RISC-V Fixes for 5.13-rc7

* A build fix to always build modules with the medany code model, as
  the module loader doesn't support medlow.
* A Kconfig warning fix for the SiFive errata.
* A pair of fixes that for regressions to the recent memory layout
  changes.
* A fix for the FU740 device tree.

----------------------------------------------------------------
David Abdurachmanov (1):
      riscv: dts: fu740: fix cache-controller interrupts

Jisheng Zhang (2):
      riscv: kasan: Fix MODULES_VADDR evaluation due to local variables' name
      riscv: Ensure BPF_JIT_REGION_START aligned with PMD size

Khem Raj (1):
      riscv32: Use medany C model for modules

Randy Dunlap (1):
      riscv: sifive: fix Kconfig errata warning

 Documentation/riscv/vm-layout.rst          |  4 ++--
 arch/riscv/Kconfig.socs                    |  1 +
 arch/riscv/Makefile                        |  2 +-
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi |  2 +-
 arch/riscv/include/asm/pgtable.h           |  5 ++---
 arch/riscv/mm/kasan_init.c                 | 10 +++++-----
 6 files changed, 12 insertions(+), 12 deletions(-)