[RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations

[Bin Meng]

On Sun, Jun 13, 2021 at 12:07 AM Anup Patel <anup.patel at wdc.com> wrote:
>
> The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
> S-mode but readonly for M-mode so we clear this bit only when using

nits: read-only

> SBI IPI operations.
>
> Signed-off-by: Anup Patel <anup.patel at wdc.com>
> ---
>  arch/riscv/kernel/sbi.c | 8 +++++++-
>  arch/riscv/kernel/smp.c | 2 --
>  2 files changed, 7 insertions(+), 3 deletions(-)
>

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>