rebased ASID-based tlbflush

[Guo Ren]

I've just tested your for-next, but:

 LD      .tmp_vmlinux.kallsyms1
/home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
mm/vmalloc.o: in function `.L0 ':
vmalloc.c:(.text+0x2bd2): undefined reference to `pud_clear_huge'
/home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
mm/vmalloc.o: in function `.L1225':
vmalloc.c:(.text+0x2cac): undefined reference to `pud_clear_huge'
Makefile:1191: recipe for target 'vmlinux' failed

I quick fixup with the simple patch:
diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
index 738dc6f3530f..b1fbd575cbac 100644
--- a/arch/riscv/mm/pgtable.c
+++ b/arch/riscv/mm/pgtable.c
@@ -25,6 +25,14 @@ int pmd_clear_huge(pmd_t *pmd)
 }
 #endif

+int pud_clear_huge(pud_t *pudp)
+{
+       if (!pud_leaf(READ_ONCE(*pudp)))
+               return 0;
+       pud_clear(pudp);
+       return 1;
+}
+
 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
 {
        pte_t *pte;

I think it's from:
commit 14512690a16537527dacf0f5cd3d2263be317f35
Author: Liu Shixin <liushixin2 at huawei.com>
Date:   Sat Jun 5 13:48:37 2021 +0800

    riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT

    This sets the HAVE_ARCH_HUGE_VMAP option. Enable pmd vmap support and
    define the required page table functions(Currently, riscv has only
    three-level page tables support for 64BIT).

    Signed-off-by: Liu Shixin <liushixin2 at huawei.com>
    Signed-off-by: Palmer Dabbelt <palmerdabbelt at google.com>

On Sun, Jun 13, 2021 at 8:47 AM Palmer Dabbelt <palmerdabbelt at google.com> wrote:
>
> On Sun, 06 Jun 2021 08:20:48 PDT (-0700), Christoph Hellwig wrote:
> > Hi all,
> >
> > this is what I think is a resonable set of patches for the ASID based
> > flushing, largely based on the work from Guo and thus attributed to him.
>
> Thanks, these are on for-next.



-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/