[PATCH RFC 0/3] riscv: Add DMA_COHERENT support
hch at lst.de
Tue Jun 8 08:32:03 PDT 2021
On Tue, Jun 08, 2021 at 03:00:17PM +0000, David Laight wrote:
> It is almost impossible to interface to many ethernet chips without
> either coherent or uncached memory for the descriptor rings.
> The status bits on the transmit ring are particularly problematic.
> The receive ring can be done with writeback+invalidate provided you
> fill a cache line at a time.
It is horrible, but it has been done. Take a look at:
More information about the linux-riscv