[PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes

[Conor.Dooley at microchip.com]

On 16/06/2021 07:02, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Bin Meng <bin.meng at windriver.com>
>
> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>
> Signed-off-by: Bin Meng <bin.meng at windriver.com>
> ---
>
>   arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
>   1 file changed, 5 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index b9819570a7d1..ee54878b3f89 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -17,7 +17,6 @@ cpus {
>                  #size-cells = <0>;
>
>                  cpu at 0 {
> -                       clock-frequency = <0>;
>                          compatible = "sifive,e51", "sifive,rocket0", "riscv";
>                          device_type = "cpu";
>                          i-cache-block-size = <64>;
> @@ -35,7 +34,6 @@ cpu0_intc: interrupt-controller {
>                  };
>
>                  cpu at 1 {
> -                       clock-frequency = <0>;
>                          compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>                          d-cache-block-size = <64>;
>                          d-cache-sets = <64>;
> @@ -62,7 +60,6 @@ cpu1_intc: interrupt-controller {
>                  };
>
>                  cpu at 2 {
> -                       clock-frequency = <0>;
>                          compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>                          d-cache-block-size = <64>;
>                          d-cache-sets = <64>;
> @@ -89,7 +86,6 @@ cpu2_intc: interrupt-controller {
>                  };
>
>                  cpu at 3 {
> -                       clock-frequency = <0>;
>                          compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>                          d-cache-block-size = <64>;
>                          d-cache-sets = <64>;
> @@ -116,7 +112,6 @@ cpu3_intc: interrupt-controller {
>                  };
>
>                  cpu at 4 {
> -                       clock-frequency = <0>;
>                          compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>                          d-cache-block-size = <64>;
>                          d-cache-sets = <64>;
> --
> 2.25.1
>

Reviewed-by: conor dooley<conor.dooley at microchip.com>

> _______________________________________________
> linux-riscv mailing list
> linux-riscv at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv