[PATCH v18 01/16] clk: Add RISC-V Canaan Kendryte K210 clock driver

[Damien Le Moal]

On 2021/02/11 11:29, Stephen Boyd wrote:
> Quoting Damien Le Moal (2021-02-09 20:32:34)
>> On 2021/02/10 12:15, Damien Le Moal wrote:
>>> On 2021/02/10 10:24, Stephen Boyd wrote:
>>>>> +               return;
>>>>> +       }
>>>>> +
>>>>> +       in0 = of_clk_get_parent_name(np, 0);
>>>>
>>>> I'm still lost why we need to get the clk parent name here vs. using the
>>>> index approach and using clk_parent_data. There were some comments about
>>>> #clock-cells which didn't make sense to me. The fixed rate clk in DT
>>>> should have #clock-cells as it is a clk.
>>>
>>> It is like this because I could not get your suggested approach to work. I am
>>> using clk_parent_data[]->hw for specifying the parents of the clocks registered
>>> by this driver. But using this data structure, I failed to figure out how to
>>> specify the "in0" clock as a parent without using the clock name itself. The
>>> other option I see is using fw_name (I do not understand that one) and hw, but I
>>> do not have that pointer since the clock is registered by the common framework.
>>> What am I missing here ?
>>
>> Revisiting this, I think I got it. All I need to to is set ".index = 0" in
>> clk_parent_data[] of the clocks that have in0 as a parent. Very simple indeed. I
>> removed the ino clock name stuff.
>> Testing and sending out v19.
> 
> Great!

I posted v19 yesterday. I hope you got it.
Your review/ack would be very welcome :)

Thanks !


-- 
Damien Le Moal
Western Digital Research