[PATCH v19 04/17] dt-bindings: update risc-v cpu properties

Damien Le Moal damien.lemoal at wdc.com
Wed Feb 10 00:02:17 EST 2021

The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip
version using a draft verion of the RISC-V ISA specifications. To avoid
any confusion with CPU cores using stable specifications, add the
compatible string "canaan,k210" for this SoC CPU cores.

Also add the "riscv,none" value to the mmu-type property to allow a DT
to indicate that the CPU being described does not have an MMU or that
it has an MMU that is not usable (which is the case for the K210 SoC).

Cc: Paul Walmsley <paul.walmsley at sifive.com>
Cc: Rob Herring <robh at kernel.org>
Cc: devicetree at vger.kernel.org
Signed-off-by: Damien Le Moal <damien.lemoal at wdc.com>
Reviewed-by: Atish Patra <atish.patra at wdc.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
Acked-by: Rob Herring <robh at kernel.org>
 Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index eb6843f69f7c..e534f6a7cfa1 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -39,6 +39,7 @@ properties:
               - sifive,u74
               - sifive,u5
               - sifive,u7
+              - canaan,k210
           - const: riscv
       - const: riscv    # Simulator only
@@ -56,6 +57,7 @@ properties:
       - riscv,sv32
       - riscv,sv39
       - riscv,sv48
+      - riscv,none

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