[PATCH v16 03/16] dt-bindings: update risc-v cpu properties

Rob Herring robh at kernel.org
Fri Feb 5 14:47:11 EST 2021

On Fri, 05 Feb 2021 15:58:14 +0900, Damien Le Moal wrote:
> The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip
> version using a draft verion of the RISC-V ISA specifications. To avoid
> any confusion with CPU cores using stable specifications, add the
> compatible string "canaan,k210" for this SoC CPU cores.
> Also add the "riscv,none" value to the mmu-type property to allow a DT
> to indicate that the CPU being described does not have an MMU or that
> it has an MMU that is not usable (which is the case for the K210 SoC).
> Cc: Paul Walmsley <paul.walmsley at sifive.com>
> Cc: Rob Herring <robh at kernel.org>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Damien Le Moal <damien.lemoal at wdc.com>
> Reviewed-by: Atish Patra <atish.patra at wdc.com>
> Reviewed-by: Anup Patel <anup at brainfault.org>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Rob Herring <robh at kernel.org>

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