[PATCH v14 04/16] dt-bindings: update sifive plic compatible string

[Damien Le Moal]

On Tue, 2021-02-02 at 10:26 -0800, Atish Patra wrote:
> On Tue, Feb 2, 2021 at 2:37 AM Damien Le Moal <damien.lemoal at wdc.com> wrote:
> > 
> > Add the compatible string "canaan,k210-plic" to the Sifive plic bindings
> > to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan
> > Kendryte K210 SoC. The description is also updated to reflect this
> > change, that is, that SoCs from other vendors may also use this plic
> > implementation.
> > 
> > Cc: Paul Walmsley <paul.walmsley at sifive.com>
> > Cc: Rob Herring <robh at kernel.org>
> > Cc: devicetree at vger.kernel.org
> > Signed-off-by: Damien Le Moal <damien.lemoal at wdc.com>
> > ---
> >  .../sifive,plic-1.0.0.yaml                    | 20 ++++++++++++-------
> >  1 file changed, 13 insertions(+), 7 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > index b9a61c9f7530..3db86d329e1e 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > @@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> >  title: SiFive Platform-Level Interrupt Controller (PLIC)
> > 
> >  description:
> > -  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
> > -  (PLIC) high-level specification in the RISC-V Privileged Architecture
> > -  specification. The PLIC connects all external interrupts in the system to all
> > -  hart contexts in the system, via the external interrupt source in each hart.
> > +  SiFive other RISC-V and other SoCs include an implementation of the
> > +  Platform-Level Interrupt Controller (PLIC) high-level specification in
> > +  the RISC-V Privileged Architecture specification. The PLIC connects all
> 
> The latest privilege spec doesn't specify PLIC anymore.

I kept the text as it was, only adding the reference to the K210. A separate
patch should fix this. I will fix the typo at the beginning of the sentence
though (just noticed it now).

> 
> > +  external interrupts in the system to all hart contexts in the system, via
> > +  the external interrupt source in each hart.
> > 
> >    A hart context is a privilege mode in a hardware execution thread. For example,
> >    in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
> > @@ -41,9 +42,14 @@ maintainers:
> > 
> >  properties:
> >    compatible:
> > -    items:
> > -      - const: sifive,fu540-c000-plic
> > -      - const: sifive,plic-1.0.0
> > +    oneOf:
> > +      - items:
> > +          - const: sifive,fu540-c000-plic
> > +          - const: sifive,plic-1.0.0
> > +
> > +      - items:
> > +          - const: canaan,k210-plic
> > +          - const: sifive,plic-1.0.0
> > 
> >    reg:
> >      maxItems: 1
> > --
> > 2.29.2
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> 
> other than that,
> 
> Reviewed-by: Atish Patra <atish.patra at wdc.com>
> 

-- 
Damien Le Moal
Western Digital Research