[PATCH v1 2/2] dt-bindings: riscv: Add DT binding for RISC-V ISA extensions

[Atish Patra]

On Fri, Dec 24, 2021 at 3:25 PM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>
> On 24 Dec 2021, at 21:16, Atish Patra <atishp at atishpatra.org> wrote:
> >
> > RISC-V ISA extensions can be single letter or multi-letter names.
> > The single letter extensions are mostly base extensions and encoded in
> > "riscv,isa" DT property. However, parsing the multi-letter extensions
> > via the isa string is cumbersome and is not scalable.
> >
> > Add a new DT node for multi-letter extensions.
> >
> > Signed-off-by: Atish Patra <atishp at rivosinc.com>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index aa5fb64d57eb..6c4eecf389a9 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -78,6 +78,15 @@ properties:
> >       - rv64imac
> >       - rv64imafdc
> >
> > +  riscv,isa-ext:
> > +    description:
> > +      Identifies the specific RISC-V instruction set architecture extensions
> > +      supported by one or multiple harts. All the multi-letter extensions
> > +      should be listed here as a boolean property. This subnode can be under
> > +      /cpus or under individual cpu node. In case of former, it represent
> > +      the common ISA extensions for all harts. The name of the boolean property
> > +      must match the actual ISA extension name in all lowercase format.
>
> I don’t see why this needs explicitly calling out, that’s true in
> general of cpu node properties (3.8p4 of the Devicetree spec v0.4-rc1 /
> v0.3-40-g7e1cc17), not that I like it.
>

Thanks for pointing it out. I did not realize the DT specification
already has a paragraph
about this. I will update the description in the next version.

> Jess
>


-- 
Regards,
Atish