[RFC PATCH v3 05/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings
Rob Herring
robh at kernel.org
Tue Aug 31 18:24:28 PDT 2021
On Mon, Aug 30, 2021 at 09:47:23AM +0530, Anup Patel wrote:
> We add DT bindings documentation for the ACLINT MSWI and SSWI
> devices found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <anup.patel at wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
> .../riscv,aclint-swi.yaml | 95 +++++++++++++++++++
> 1 file changed, 95 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> new file mode 100644
> index 000000000000..68563259ae24
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> @@ -0,0 +1,95 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT Software Interrupt Devices
> +
> +maintainers:
> + - Anup Patel <anup.patel at wdc.com>
> +
> +description:
> + RISC-V SOCs include an implementation of the M-level software interrupt
> + (MSWI) device and the S-level software interrupt (SSWI) device defined
> + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
> +
> + The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT
> + specification located at
> + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> + The ACLINT MSWI and SSWI devices directly connect to the M-level and
> + S-level software interrupt lines of various HARTs (or CPUs) respectively
> + so the RISC-V per-HART (or per-CPU) local interrupt controller is the
> + parent interrupt controller for the ACLINT MSWI and SSWI devices.
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - riscv,aclint-mswi
> +
> + - items:
> + - enum:
> + - riscv,aclint-sswi
All this can be just:
enum:
- riscv,aclint-mswi
- riscv,aclint-sswi
However...
> +
> + description:
> + For ACLINT MSWI devices, it should be "riscv,aclint-mswi" OR
> + "<vendor>,<chip>-aclint-mswi".
> + For ACLINT SSWI devices, it should be "riscv,aclint-sswi" OR
> + "<vendor>,<chip>-aclint-sswi".
s/OR/AND/
There must be a compatible for the implementation. Unless RiscV
implementations of specs are complete describing all clocks, power
domains, resets, etc. and are quirk free.
But don't write free form constraints...
> +
> + reg:
> + maxItems: 1
> +
> + "#interrupt-cells":
> + const: 0
> +
> + interrupts-extended:
> + minItems: 1
> + maxItems: 4095
> +
> + interrupt-controller: true
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> +examples:
> + - |
> + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
> +
> + interrupt-controller at 2000000 {
> + compatible = "riscv,aclint-mswi";
> + interrupts-extended = <&cpu1intc 3>,
> + <&cpu2intc 3>,
> + <&cpu3intc 3>,
> + <&cpu4intc 3>;
> + reg = <0x2000000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + };
> +
> + - |
> + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
> +
> + interrupt-controller at 2100000 {
> + compatible = "riscv,aclint-sswi";
> + interrupts-extended = <&cpu1intc 1>,
> + <&cpu2intc 1>,
> + <&cpu3intc 1>,
> + <&cpu4intc 1>;
> + reg = <0x2100000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + };
> +...
> --
> 2.25.1
>
>
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