[RFC][PATCH] locking: Generic ticket-lock
peterz at infradead.org
Wed Apr 14 13:45:43 BST 2021
On Wed, Apr 14, 2021 at 12:16:38PM +0200, Peter Zijlstra wrote:
> On Wed, Apr 14, 2021 at 11:05:24AM +0200, Peter Zijlstra wrote:
> > That made me look at the qspinlock code, and queued_spin_*lock() uses
> > atomic_try_cmpxchg_acquire(), which means any arch that uses qspinlock
> > and has RCpc atomics will give us massive pain.
> > Current archs using qspinlock are: x86, arm64, power, sparc64, mips and
> > openrisc (WTF?!).
> > Of those, x86 and sparc are TSO archs with SC atomics, arm64 has RCsc
> > atomics, power has RCtso atomics (and is the arch we all hate for having
> > RCtso locks).
> > Now MIPS has all sorts of ill specified barriers, but last time looked
> > at it it didn't actually use any of that and stuck to using smp_mb(), so
> > it will have RCsc atomics.
> > /me goes look at wth openrisc is.. doesn't even appear to have
> > asm/barrier.h :-/ Looking at wikipedia it also doesn't appear to
> > actually have hardware ...
> FWIW this is broken, anything SMP *MUST* define mb(), at the very least.
As near as I can tell this should do. The arch spec only lists this one
instruction and the text makes it sound like a completion barrier.
arch/openrisc/include/asm/barrier.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/openrisc/include/asm/barrier.h b/arch/openrisc/include/asm/barrier.h
new file mode 100644
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#define mb() asm volatile ("l.msync" ::: "memory")
+#endif /* __ASM_BARRIER_H */
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