[PATCH] riscv: locks: introduce ticket-based spinlock implementation

David Laight David.Laight at ACULAB.COM
Tue Apr 13 11:54:36 BST 2021

From: Catalin Marinas
> Sent: 13 April 2021 11:45
> This indeed needs some care. IIUC RISC-V has similar restrictions as arm
> here, no load/store instructions are allowed between LR and SC. You
> can't guarantee that the compiler won't spill some variable onto the
> stack.

You can probably never guarantee the compiler won't spill to stack.
Especially if someone compiles with -O0.

Which probably means that anything using LR/SC must be written in
asm and the C wrappers disabled.


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