[RFC PATCH v7 17/21] riscv: Initialize vector registers with proper vsetvli then it can work normally

[Greentime Hu]

It may cause an illegal instruction exception if it doesn't use vsetvli
before vmv.v.i v0, 0.

Signed-off-by: Han-Kuan Chen <hankuan.chen at sifive.com>
Signed-off-by: Greentime Hu <greentime.hu at sifive.com>
---
 arch/riscv/kernel/head.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index e97c7915ae27..74f2fd8430e0 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -375,6 +375,7 @@ ENTRY(reset_regs)
 
 	li	t1, SR_VS
 	csrs	CSR_STATUS, t1
+	vsetvli t1, x0, e8, m1
 	vmv.v.i v0, 0
 	vmv.v.i v1, 0
 	vmv.v.i v2, 0
-- 
2.28.0