[GIT PULL] RISC-V Fixes for 5.9-rc2

[Anup Patel]

On Fri, Sep 4, 2020 at 9:33 PM Christoph Hellwig <hch at infradead.org> wrote:
>
> On Fri, Sep 04, 2020 at 07:26:41PM +0530, Anup Patel wrote:
> > On Fri, Sep 4, 2020 at 6:30 PM Christoph Hellwig <hch at infradead.org> wrote:
> > >
> > > On Fri, Sep 04, 2020 at 08:58:25PM +0800, Qiu Wenbo wrote:
> > > > I can confirm this patch also breaks K210 support. It seems that
> > > > csr_read(CSR_TIME) will trigger an illegal instruction exception on K210.
> > >
> > > CSR_TIME is trapped by just about every implementation I know (which is
> > > explicitly allowed by the spec).  That is why we should never use it
> > > from common M-mode code.
> >
> > Finally, I was able to replicate this issue by manually hacking QEMU to
> > not emulatie TIME CSR for virt machine.
> >
> > It seems this issue is only seen on older QEMU and Kendrtye K210.
>
> You'd also see it when running nommu on Sifivie or just about any
> hardware.  Whoever implement the TIME CSR for qemu made a mistake IMHO
> as it doesn't match how most real hardware behaves.

There are quite a few RISCV systems who implement TIME CSR in
hardware due to performance gains (10+ %).

The QEMU virt machine does not represent real-world HW so we
should emulate all possible HW optimizations in QEMU virt machine.

On other hand, the QEMU sifive_u machine correctly matches the
real-world SiFive Unleashed in-context of TIME CSR and other HW
features.

IMHO, we need nommu defconfig for SiFive Unleashed so that we
can try NoMMU kernel on both QEMU virt and QEMU sifive_u machine.

Regards,
Anup