[PATCH 3/3] edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs

[Yash Shah]

> -----Original Message-----
> From: Borislav Petkov <bp at alien8.de>
> Sent: 31 August 2020 14:22
> To: Yash Shah <yash.shah at openfive.com>
> Cc: robh+dt at kernel.org; palmer at dabbelt.com; Paul Walmsley ( Sifive)
> <paul.walmsley at sifive.com>; mchehab at kernel.org; tony.luck at intel.com;
> aou at eecs.berkeley.edu; james.morse at arm.com; rrichter at marvell.com;
> devicetree at vger.kernel.org; linux-riscv at lists.infradead.org; linux-
> kernel at vger.kernel.org; linux-edac at vger.kernel.org; Sachin Ghadi
> <sachin.ghadi at openfive.com>
> Subject: Re: [PATCH 3/3] edac: sifive: Add EDAC support for Memory
> Controller in SiFive SoCs
> 
> [External Email] Do not click links or attachments unless you recognize the
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> 
> > Subject: Re: [PATCH 3/3] edac: sifive: Add EDAC support for Memory
> > Controller in SiFive SoCs
> 
> Fix subject prefix: "EDAC/sifive: ..."
> 
> On Tue, Aug 25, 2020 at 05:36:22PM +0530, Yash Shah wrote:
> > Add Memory controller EDAC support in exisiting SiFive platform EDAC
> 
> s/in exisiting/to the/
> 
> > driver. It registers for notifier events from the SiFive DDR
> > controller driver for DDR ECC events.
> 
> Simplify:
> 
> "It registers for ECC notifier events from the memory controller."
> 
> > Signed-off-by: Yash Shah <yash.shah at sifive.com>
> > ---
> >  drivers/edac/Kconfig       |   2 +-
> >  drivers/edac/sifive_edac.c | 117
> > +++++++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 118 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index
> > 7b6ec30..f8b3b53 100644
> > --- a/drivers/edac/Kconfig
> > +++ b/drivers/edac/Kconfig
> > @@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
> >
> >  config EDAC_SIFIVE
> >       bool "Sifive platform EDAC driver"
> > -     depends on EDAC=y && SIFIVE_L2
> > +     depends on EDAC=y && (SIFIVE_L2 || SIFIVE_DDR)
> >       help
> >         Support for error detection and correction on the SiFive SoCs.
> >
> > diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
> > index 3a3dcb1..cf032685 100644
> > --- a/drivers/edac/sifive_edac.c
> > +++ b/drivers/edac/sifive_edac.c
> > @@ -11,14 +11,120 @@
> >  #include <linux/platform_device.h>
> >  #include "edac_module.h"
> >  #include <soc/sifive/sifive_l2_cache.h>
> > +#include <soc/sifive/sifive_ddr.h>
> >
> >  #define DRVNAME "sifive_edac"
> > +#define SIFIVE_EDAC_MOD_NAME "Sifive ECC Manager"
> 
> s/SIFIVE_EDAC_MOD_NAME/EDAC_MOD_NAME/g
> 
> like the other EDAC drivers.
> 

Sure, will make all the above suggested textual changes in v2.

> ...
> 
> > +static int ecc_mc_register(struct platform_device *pdev) {
> > +     struct sifive_edac_mc_priv *p;
> > +     struct edac_mc_layer layers[1];
> > +     int ret;
> > +
> > +     p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
> > +     if (!p)
> > +             return -ENOMEM;
> > +
> > +     p->notifier.notifier_call = ecc_mc_err_event;
> > +     platform_set_drvdata(pdev, p);
> > +
> > +     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
> > +     layers[0].size = 1;
> > +     layers[0].is_virt_csrow = true;
> > +
> > +     p->mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
> > +     if (!p->mci) {
> > +             dev_err(&pdev->dev, "Failed mem allocation for mc instance\n");
> > +             return -ENOMEM;
> > +     }
> > +
> > +     p->mci->pdev = &pdev->dev;
> > +     /* Initialize controller capabilities */
> > +     p->mci->mtype_cap = MEM_FLAG_DDR4;
> > +     p->mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
> > +     p->mci->edac_cap = EDAC_FLAG_SECDED;
> > +     p->mci->scrub_cap = SCRUB_UNKNOWN;
> > +     p->mci->scrub_mode = SCRUB_HW_PROG;
> > +     p->mci->ctl_name = dev_name(&pdev->dev);
> > +     p->mci->dev_name = dev_name(&pdev->dev);
> > +     p->mci->mod_name = SIFIVE_EDAC_MOD_NAME;
> > +     p->mci->ctl_page_to_phys = NULL;
> > +
> > +     /* Interrupt feature is supported by cadence mc */
> > +     edac_op_state = EDAC_OPSTATE_INT;
> > +
> > +     ret = edac_mc_add_mc(p->mci);
> > +     if (ret) {
> > +             edac_printk(KERN_ERR, SIFIVE_EDAC_MOD_NAME,
> > +                         "Failed to register with EDAC core\n");
> > +             goto err;
> > +     }
> > +
> > +#ifdef CONFIG_SIFIVE_DDR
> 
> It seems all that ifdeffery can be replaced with
> 
>         if (IS_ENABLED(CONFIG_...))

Yes, will replace all the ifdeffery in v2
Thanks for the review.

- Yash

> 
> Thx.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> https://people.kernel.org/tglx/notes-about-netiquette