[PATCH 5/6] dt-bindings: add bindings for polarfire soc system controller
conor.dooley at microchip.com
conor.dooley at microchip.com
Thu Nov 19 12:04:41 EST 2020
From: Conor Dooley <conor.dooley at microchip.com>
Add device tree bindings for the MSS system controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
.../microchip,mpfs_sys_controller.yaml | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml
new file mode 100644
index 000000000000..a1c5bba5068c
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs_sys_controller.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip MPFS system controller
+
+maintainers:
+ - Conor Dooley <conor.dooley at microchip.com>
+
+properties:
+ compatible:
+ const: microchip,polarfire-soc-sys-controller # PolarFire
+
+ mbox-names:
+ maxItems: 1
+ description: name of the mailbox controller device node
+
+ mboxes:
+ maxItems: 1
+ description: |
+ phandle and index of the mailbox controller device node. It must be 0 (hardware supports only one channel).
+
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+required:
+ - compatible
+ - mbox-names
+ - "#address-cells"
+ - "#size-cells"
+ - "mboxes"
+
+unevaluatedProperties: false
+additionalProperties: false
+
+examples:
+ - |
+ syscontroller at 37020000 {
+ compatible = "microchip,polarfire-soc-sys-controller";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ mbox-names = "mbox-mpfs";
+ mboxes = <&mbox 0>;
+ };
--
2.17.1
More information about the linux-riscv
mailing list