[PATCH 18/32] riscv: Add Kendryte K210 SoC clock driver

[Damien Le Moal]

On Sat, 2020-11-07 at 08:48 -0500, Sean Anderson wrote:
[...]
> > +static void k210_pll_disable_hw(struct k210_pll *pll)
> > +{
> > +	unsigned long flags;
> > +	u32 reg;
> > +
> > +	/*
> > +	 * Bypassing before powering off is important so child clocks don't stop
> > +	 * working. This is especially important for pll0, the indirect parent
> > +	 * of the cpu clock.
> > +	 */
> 
> Did you get the bypass bit to work? I'm still having to bypass via
> re-parenting ACLK in U-boot. Perhaps it is only necessary if you change
> the rate as well?

Nope. No luck there. The Kendryte SDK also does a reparenting of ACLK to IN0
when changing the PLL rate. So I guess I should remove the comment maybe.

In any case, this is all running with the default rates, except for PLL1 rate
which is changed in early init code to end up with matching frequencies for all
SRAM banks. So I do not think that the not-so-effective bypass is an issue
here.

-- 
Damien Le Moal
Western Digital