[PATCH 06/32] spi: dw: Add support for the Kendryte K210 SoC

[Damien Le Moal]

On Sat, 2020-11-07 at 08:31 -0500, Sean Anderson wrote:
> On 11/7/20 3:13 AM, Damien Le Moal wrote:
> > The DW SPI master of the Kendryte K210 RISC-V SoC uses the 32-bits
> > ctrlr0 register format. This SoC is also quite slow and gets significant
> > SD card performance improvements from using no-delay polled transfers.
> > Add the dw_spi_k210_init() function tied to the
> > "canaan,kendryte-k210-spi" compatible string to set the
> > DW_SPI_CAP_DFS_32 and DW_SPI_CAP_POLL_NODELAY DW SPI capability fields
> > for this SoC.
> > 
> > Signed-off-by: Damien Le Moal <damien.lemoal at wdc.com>
> > ---
> >  drivers/spi/spi-dw-mmio.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
> > index 3f1bc384cb45..a00def6c5b39 100644
> > --- a/drivers/spi/spi-dw-mmio.c
> > +++ b/drivers/spi/spi-dw-mmio.c
> > @@ -223,6 +223,14 @@ static int dw_spi_keembay_init(struct platform_device *pdev,
> >  	return 0;
> >  }
> >  
> > 
> > 
> > 
> > +static int dw_spi_k210_init(struct platform_device *pdev,
> > +			    struct dw_spi_mmio *dwsmmio)
> > +{
> > +	dwsmmio->dws.caps = DW_SPI_CAP_DFS_32 | DW_SPI_CAP_POLL_NODELAY;
> 
> Can't you do runtime detection of DFS_32 in probe?

Done ! Sending that in V2 (I will split the spi dw from the rest of the
series).



-- 
Damien Le Moal
Western Digital