[PATCH 1/3] dt-bindings: riscv: Add DT documentation for SiFive Bus Error Unit
Yash Shah
yash.shah at sifive.com
Thu Nov 12 07:00:55 EST 2020
Add DT json-schema for SiFive Bus Error unit present in FU740-C000 chip
Signed-off-by: Yash Shah <yash.shah at sifive.com>
---
.../devicetree/bindings/riscv/sifive-beu.yaml | 47 ++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-beu.yaml
diff --git a/Documentation/devicetree/bindings/riscv/sifive-beu.yaml b/Documentation/devicetree/bindings/riscv/sifive-beu.yaml
new file mode 100644
index 0000000..4697787
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive-beu.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sifive-beu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive BUS Error Unit
+
+maintainers:
+ - Yash Shah <yash.shah at sifive.com>
+ - Paul Walmsley <paul.walmsley at sifive.com>
+
+description:
+ The Bus-Error Unit (BEU) is a per-processor device that records erroneous
+ events and reports them using platform-level and hart-local interrupts. The
+ BEU can be configured to generate interrupts on correctable memory errors,
+ uncorrectable memory errors, and/or TileLink bus errors.
+ All the properties in ePAPR/DeviceTree specification applies for this platform.
+
+properties:
+ compatible:
+ items:
+ - const: sifive,fu740-c000-beu
+ - const: sifive,beu0
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - interrupts
+ - reg
+
+examples:
+ - |
+ bus-error-unit at 1700000 {
+ compatible = "sifive,fu740-c000-beu", "sifive,beu0";
+ reg = <0x1700000 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <65>;
+ };
--
2.7.4
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